not for new design recommended replacement a6810 bimos ii 10-bit serial-input, latched source drivers with active-dmos pull-downs always order by complete part number, e.g., ucn5810af . the ucn5810af and ucn5810lwf combine a 10-bit cmos shift register and accompanying data latches, control circuitry, bipolar sourcing outputs with dmos active pull-downs. designed primarily to drive vacuum- fluorescent displays, the 60 v and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. the ucn5810af/lwf feature reduced supply requirements (active dmos pull- downs) and lower saturation voltages when compared with the original ucn5810a. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 5 v supply, they will operate to at least 3.3 mhz. at 12 v, higher speeds are possible. use with ttl may require appropriate pull-up resistors to ensure an input logic high. a cmos serial data output enables cascade connections in applications requiring additional drive lines. similar devices are available as the ucn5811a (12 bits), ucn5812af/epf (20 bits), and ucn5818af/epf (32 bits). the ucn5810af/lwf output source drivers are npn darlingtons capable of sourcing up to 40 ma. the dmos active pull-downs are capable of sinking up to 15 ma. for inter-digit blanking, all of the output drivers can be disabled and the dmos sink drivers turned on by the blanking input high. the ucn5810af is furnished in an 18-pin dual in-line plastic package. the ucn5810lwf is furnished in a wide-body, small-outline plastic package (soic) with gull-wing leads. copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to source 25 ma from all outputs continuously, over the entire operating temperature range. all devices are also available for operation between -40 c and +85 c. to order, change the prefix from ucn to ucq. features high-speed source drivers 60 v minimum output breakdown improved replacements for tl4810b ucn5810af data sheet 26182.24e 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 serial data out load supply serial data in blanking logic supply strobe ground clock clk v st blnk dd bb v out 9 out 10 out 1 out 2 out 3 dwg. pp-029 out 8 out 7 out 6 out 5 out 4 1 latches register register latches absolute maximum ratings at t a = 25 c logic supply voltage, v dd ..................... 15 v driver supply voltage, v bb .................... 60 v continuous output current range, i out .......................... -40 ma to +15 ma input voltage range, v in ........................ -0.3 v to v dd + 0.3 v package power dissipation, p d (ucn5810af) ........................... 2.08 w* (ucn5810lwf) ........................ 1.33 w* operating temperature range, t a .................................. -20 c to +85 c storage temperature range, t s ................................ -55 c to +150 c *derate linearly to 0 w at +150 c. caution: cmos devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. note that the ucn5810af (dual in-line package) and ucn5810lwf (small-outline ic package) are electrically identical and share a common terminal number assignment. low output saturation voltages low-power cmos logic and latches to 3.3 mhz data input rate active dmos pull-downs 5810 -f
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 functional block diagram typical input circuit typical output driver dwg. no. a-14,219 50 75 100 125 150 2.5 0.5 0 ambient temperature in c 2.0 1.5 1.0 25 dwg. gp-018c suffix 'a', r = 60 c/w ja suffix 'lw', r = 94 c/w ja allowable package power dissipation in watts 11 12 13 14 15 17 10 16 18 serial data out load supply serial data in blanking out 9 out 10 out 1 out 2 out 3 dwg. pp-029-1 1 2 3 8 9 4 5 6 7 logic supply strobe ground clock clk v st blnk dd bb v out 8 out 7 out 6 out 5 out 4 latches register register latches ucn5810lwf v out bb n mos bipolar out 1 out 2 ground dwg. fp-013-1 out 3 out n clock serial data in strobe blanking serial data out serial-parallel shift register latches v dd v bb logic supply load supply dwg. ep-010-4a in v dd copyright ?1988, 2004 allegro microsystems, inc.
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs www.allegromicro.com limits @ v dd = 5 v limits @ v dd = 12 v characteristic symbol test conditions mln. typ. max. min. typ. max. units output leakage current i cex v out = 0 v, t a = +70 c -5.0 -15 -5.0 -15 a output voltage v out(1) i out = -25 ma 58 58.5 58 58.5 v v out(0) i out = 1 ma 1.0 1.5 v i out = 2 ma 1.0 1.5 v output pull-down current i out(0) v out = 5 v to v bb 2.0 3.5 ma v out = 20 v to v bb 8.013 ma input voltage v in(1) 3.5 5.3 10.5 12.3 v v in(0) -0.3 +0.8 -0.3 +0.8 v input current i in(1) v in = v dd 100 240 a i in(0) v in = 0.8 v -0.05 -0.5 -0.1 -1.0 a serial data output voltage v out(1) i out = -200 a 4.5 4.7 11.7 11.8 v v out(0) i out = 200 a 200 250 100 200 mv maximum clock frequency f clk 3.3* mhz supply current i dd(1) all outputs high 100 300 200 500 a i dd(0) all outputs low 100 300 200 500 a i bb(1) outputs high, no load 0.7 2.0 0.7 2.0 ma i bb(0) outputs low 10 100 10 100 a blanking to output delay t phl c l = 30 pf, 50% to 50% 2000 1000 ns t plh c l = 30 pf, 50% to 50% 1000 850 ns output fall time t f c l = 30 pf, 90% to 10% 1450 650 ns output rise time t r c l = 30 pf, 10% to 90% 650 700 ns negative current is defined as coming out of (sourcing) the specified device pin. * operation at a clock frequency greater than the specified minimum value is possible but not warranted. electrical characteristics at t a = +25 c, v bb = 60 v unless otherwise noted.
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 truth table serial shift register contents serial latch contents output contents data clock data strobe input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n blanklng i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n lp 1 p 2 p 3 ... p n-1 p n x x x ... x x h l l l ... l l l = low logic level h = high logic level x = irrelevant p = present state r = previous state serial data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data out- put. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is trans- ferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the blanking input be high during serial data entry. when the blanking input is high, the output source drivers are disabled (off); the dmos sink drivers are on. the information stored in the latches is not affected by the blanking input. with the blanking input low, the outputs are controlled by the state of their respective latches. timing requirements (t a = +25 c,v dd = 5 v, logic levels are v dd and ground) a. minimum data active time before clock pulse (data set-up time) .......................................................................... 75 ns b. minimum data active time after clock pulse (data hold time) ............................................................................. 75 ns c. minimum data pulse width ................................................................ 150 ns d. minimum clock pulse width ............................................................... 150 ns e. minimum time between clock activation and strobe ....................... 300 ns f. minimum strobe pulse width ............................................................. 100 ns g. typical time between strobe activation and output transistion ......................................................................... 500 ns timing is representative of a 3.3 mhz clock. higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. e f clock data in strobe blanking out n a d b c g dwg. no. a-12,649a
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs www.allegromicro.com ucn5810af dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 21 devices. 0.014 0.008 0.300 bsc dwg. ma-001-18a in 0.430 max 18 1 9 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 10 0.920 0.880 0.355 0.204 7.62 bsc dwg. ma-001-18a mm 10.92 max 18 1 9 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 10 23.37 22.35
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 ucn5810lwf dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 41 devices or add ?r?to part number for tape and reel. 0 to 8 1 2 3 0.020 0.013 0.0040 min. 0.0125 0.0091 0.050 0.016 d wg. ma-008-18a in 0.050 bsc 18 10 0.419 0.394 0.2992 0.2914 0.4625 0.4469 0.0926 0.1043 0 to 8 1 18 2 3 0.51 0.33 0.10 min. 0.32 0.23 1.27 0.40 dwg. ma-008-18a mm 1.27 bsc 10 7.60 7.40 10.65 10.00 11.75 11.35 2.65 2.35
5810-f 10-bit serial-input, latched source drivers with active-dmos pull-downs www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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